In recent years, semiconductor devices each having a three-dimensional structure formed by stacking semiconductor chips were announced. For example, Kurino et al. announced an “Intelligent Image Sensor Chip with Three-Dimensional Structure” in 1999 IEDM Technical Digest published in 1999 (see Non-Patent Document 1).
This image sensor chip has a four-layer structure, where a processor array and an output circuit are located in the first semiconductor circuit layer, data latches and masking circuits are located in the second semiconductor circuit layer, amplifiers and analog-to-digital converters are located in the third semiconductor circuit layer, and an image sensor array is located in the fourth semiconductor circuit layer. The uppermost surface of the image sensor array is covered with a quartz glass layer containing a microlens array. The microlens array is formed on the surface of the quartz glass layer. A photodiode is formed as the semiconductor light-receiving element in each image sensor of the image sensor array. The respective semiconductor circuit layers constituting the four-layer structure are mechanically connected to each other with adhesive, and are electrically connected to each other with buried interconnections using conductive plugs and microbump electrodes contacted with the interconnections.
With the image sensor chip, bonding wires are not used for electrical connection among the semiconductor circuit layers. Therefore, this image sensor chip is different from a three-dimensionally structured semiconductor device fabricated by stacking and unifying semiconductor chips on a support substrate, placing bonding wires around the stacked chips, and making electrical interconnection among the semiconductor chips with the bonding wires (such a semiconductor device is conventionally known, as seen from the Non-Patent Document 1).
Moreover, Lee et al. announced an image-processing chip comprising an image sensor similar to the above-described solid-state image sensor announced by Kurino et al. in Japan Journal of Applied Physics entitled “Development of Three-Dimensional Integration Technology for Highly Parallel Image-processing Chip” published in April 2000 (see Non-Patent Document 2).
The image-processing chip of Lee et al. has approximately the same configuration as the solid-stage imaging sensor announced by Kurino et al. in the above-described treatise.
With any one of the above-described image sensor chip and the image-processing chip each having the three-dimensional stacked structure, a plurality of semiconductor wafers (which may be termed simply “wafers” below), each of which includes desired built-in semiconductor circuits, are stacked and adhered to each other and thereafter, the wafer stack thus obtained is divided into a plurality of chips by cutting (dicing), resulting in the image sensor chips or the image-processing chips. In other words, semiconductor wafers in which sets of semiconductor circuits have been respectively formed are stacked and fixed on the wafer level to thereby realize the three-dimensional stacked structure and thereafter, the stacked structure is divided to form the image sensor chips or the image-processing chips.
In addition, with the conventional image sensor chip and the conventional image-processing chip, each of the stacked semiconductor circuits stacked in the chip constitutes the “semiconductor circuit layer”.
Furthermore, a method of fabricating a semiconductor chip is disclosed in the Non-Patent Document 2. In this method, penetrating holes with ?-shaped structures whose relatively large parts and relatively small parts are respectively joined together are formed in a semiconductor substrate, where the ends of the relatively small parts are exposed to the first main surface of the substrate and the ends of the relatively large parts are exposed to the second main surface thereof. Next, the walls of the penetrating holes are covered with insulating films and then, the holes are filled with conductive material to form conductive plugs. Thereafter, a multilayer wiring structure is formed on the first main surface. It is described in the Non-Patent Document 2 that high integration level of devices, high fixing strength to the bumps and high reliability against thermal stress are obtained by this method.    Non-Patent Document 1: H. Kurino et al., “Intelligent Image Sensor Chip with Three-Dimensional Structure”, 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4, 1999    Non-Patent Document 2: K. Lee et al., “Development of Three-Dimensional Integration Technology for Highly Parallel Image-processing Chip”, Jpn. J. of Appl. Phys., Vol. 39, pp. 2473-2477, April 2000    Patent Document 1: Japanese Non-Examined Patent Publication No. 2002-110902 (FIGS. 1 and 4)    Patent Document 2: Japanese Non-Examined Patent Publication No. 2004-14657 (FIGS. 1 to 9)